Even though a fine line width is inevitably required in manufacturing a highly integrated semiconductor device, the operation voltage is fixed by the application specification.
For this reason, it can be complicated to provide a process design and a manufacturing condition for maintaining device reliability such as hot carrier injection (HCI) and negative bias temperature instability (NBTI). In particular, under the conditions of a ‘NO’ gate insulating layer having a single structure for PMOS and NMOS devices, the HCI and NBTI characteristics show opposite tendency according to an influence of nitrogen. Hence, the process design and manufacturing condition are expected to reach a limit.
A recent development incorporates a gate oxide layer of a semiconductor device including a core region and an input/output region (hereinafter, referred to as an ‘I/O region’) having two different thicknesses according to an operation voltage.
FIGS. 1A through 1B are views illustrating a method of forming a related art gate insulating layer of a semiconductor device.
Referring to FIG. 1A, a first gate oxide layer 12 is grown on an entire surface of a semiconductor substrate 11 including a field oxide layer (FOX) through a first gate oxidation process.
Referring to FIG. 1B, a photoresist layer 13 masks an I/O region during a wet etch process to the first gate oxide layer 12 in the core region.
Referring to FIG. 1C, the photoresist layer 13 is removed, and a second gate oxidation process is performed to grow a second gate oxide layer 14 with a thin thickness on the semiconductor substrate 11 in the core region. Here, as for the I/O region, since the oxidation is further performed under the first gate oxide layer 12 and thus the second gate oxide layer 14 is formed, a thick gate oxide layer including the first gate oxide layer 12 and the second gate oxide layer 14 is formed in the I/O region.
Thereafter, referring to FIG. 1D, nitrogen annealing is performed to form a nitrogen-rich (N-rich) oxide layer 15 including a large amount of nitrogen on an interface between the semiconductor substrate 11 and each of the gate oxide layers. A gate oxide layer structure including the N-rich oxide layer 15 is called a ‘NO’ gate oxide layer.
The Si—N bond made when the N-rich oxide layer 15 is formed in the NO gate oxide layer is well known for its strong resistance to a hot carrier.
However, the dual gate oxide layer structure using a nitride oxide layer has problems of trapping charge formation caused by nitrogen segregation within an oxide layer of an I/O PMOS. This trapping charge works as an obstacle in a subsequent process. That is, nitrogen trapping occurs on an interface between the first gate oxide layer and the second gate oxide layer.
When exposed to strong plasma during dry etching in a subsequent Back End of the Line (BEOL) process, nitrogen trapped on the interface may work as a site of a static charge generation by hole generation.
In general, to prevent such a phenomenon, a gate electrode is connected to an active region to distribute an impact from the design view, and condition control is made to minimize an impact of plasma from the process view.
However, the performance deterioration of a transistor is unavoidable if the design capacity with respect to impact distribution of static electricity is limited and it is difficult to set a process condition for lowering the plasma impact.
The deterioration of a PMOS transistor caused by static charges causes a threshold voltage increase (Vth increase), a saturated current reduction, and an Off leakage increase due to vertical electric field reduction.